1. Field of the Invention
The present invention relates to the field of digital-to-analog converters (DACs).
2. Prior Art
Digital-to-analog converters (DACs), used to convert digital signals to an analog voltage or current, are widely used to couple digital controllers of various types to devices responsive to analog signals. Various types of DACs are well known, with each having its own combination of strengths and weaknesses in terms of cost and performance. At the present time, there is a growing need for high-resolution DACs, e.g., 16-bit DACs. In some applications of high resolution DACs, good differential linearity and guaranteed monotonic behavior are more important than absolute accuracy. Such applications include control loops, wherein an analog response of the analog controlled parameter is digitized, processed for control purposes, and converted by a DAC to analog form to control the desired parameter by way of the closed loop. Here accuracy is provided by the closed loop itself, but resolution, stability and fast settling of the loop require the good differential linearity and monotonic behavior. Normally R-2R DACs and segment-type DAC are used for such high resolution DACs.
The resolution of untrimmed R-2R DACs is normally limited to 12-14 bits using present processing technology. If R-2R DACs are used for higher resolution purposes, they need a lot of trimming to guarantee monotonicity, making the cost of high resolution R-2R DACs very high. As for segment-type DACs, they are usually composed of strings of series-connected resistors with buffer amplifiers to prevent the second-stage resistor string from loading the first-stage resistor string. However the buffer amplifiers increase the die size and require a larger power supply. They also are sources of linearity errors.
The present invention is particularly suited for low cost and high-resolution digital-to-analog converters. The converters in accordance with the invention have a hybrid two-stage structure. The first stage is a differential segmented current DAC controlled by the MSBs (most significant bits) of input data. The second stage is a resistor string DAC controlled by the LSBs (least significant bits) of the input data to interpolate between the differential outputs of the first stage. The resistor string is directly connected to the current DAC without the need of buffer amplifiers. Instead, a replica circuit is used to prevent the second-stage resistor string from loading the first stage current DAC. Compared with prior art architectures, the invention has a simple structure, which only requires a small die area and needs a reduced number of trims compared with R-2R structures.